الفهرس 
Analog to Digital Converter BasicsOnly 14 pages are availabe for public view
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Abstract
The thesis showed at first the need for high speed ADCs, and how the continuous time Σ∆ ADCs are a good candidate for high speed applications for their low power and high speed. Then a brief introduction to the Σ∆ ADCs was given and how they evolved from discrete time to continuous time.
The thesis then presented a MATLAB based tool which can help in designing the multistage feedforward opamp either 2,3, or 4 stages. The tool can help in determining the required gain and BW of each stage according to the ADC specifications, and then the tool results were verified in CTΣ∆ simulink model (LP and BP) to show the effect of the multistage transfer function on the SNR.
A comparison between feedforward and feedback CTΣ∆ were presented, and how these architectures affect the opamp requirements. Also a jitter comparison between single bit, multibit and FIR DACs ( in case of LP) were done to show the trade offs between multibit and single bit. Then 2 design examples were presented, the first one was on 65nm for 3rd order LP CTΣ∆ using 2 taps FIR DAC, system results and simulation results showed that although FIR DACs help in decreasing metasability effect but it increase the opamp requirements (gain and Fu). The ADC uses a 6.4 GHz sampling frequency with OSR of 32, thus it has BW of 100 MHz, the ADC was designed to meet the requirements for various standards (due to its wide BW) up to 5G NR1 which requires 100 MHz BW and more than 70 dB DR (as shown in chapter 4).
The second design example was designed in 28nm-FDSOI technology and has same
Fs and OSR as example 1, but lower technology node allowed the use of single bit DAC without suffering from metastability effect. Also, this example presented a new opamp design which benefits from body bias to decrease number of transistors and hence increase the opamp BW without increasing power consumption. The 2 examples are then compared with state of the art LP CTΣ∆ in table 4.1 .
Finally the thesis presented a highly tunable wide band CTΣ∆ ADC which has a tunable center frequency from DC to 1 GHz, this was achieved by configuring the ADC coefficients to work as LP from DC to 250 MHz, then the ADC is configured to work as tunable BP from center frequency of 250 MHz to 1 GHz, the system has the advantage of low power and area when compared to other ultra wide BW ADCs (GHz BW ADCs) as [8] and [25], and has wide tuning range when compared to [35]. The system also implies a new technique to enhance the quality factor in BP case which is degraded due to limited gain, the new technique was verified analytically, then by MATLAB simulations, then by transistor level simulations.
Each block in the system was discussed to show the challenges faced during its design, corners, and layout. Then the full layout including the PADs is shown in Figure 5.20. To test for different effects which will arise from fabrication and packaging, various tests were shown to try to simulate the packaging and fabrication effects.
Finally, the proposed ADC was compared with state of the art wide BW ADCs in table 5.5, the table shows that the proposed ADC has the lowest power consumption with accepted SNR which makes it suitable for software defined radio (SDR) and mobile
applications.