الفهرس 
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Abstract
Linear voltage regulators are indispensable Analog blocks that provide a stable (reg-
ulated) power supply voltage independent of load impedance, input-voltage variations,
temperature and time. It also acts as a bulwark for the system against uctuations in
the main supply rails.
Low drop-out voltage regulators (LDOs) are a class of linear regulators that are
distinguished by their ability to maintain regulation with small dierences between
supply voltage and load voltage. LDOs are imperative in modern SOC given the con-
tinuous down scaling of the supply voltage and the SOC inherently noisy environment.
Owing to the nature of LDO as being an analog block, the design of LDO is not a
straightforward task. Analog design is an arduous process involving lots of trades os,
design variables and degrees of freedom. Finding a design point that meets all the
speci cations is intricate and even nding an optimum design point is not guaranteed.
Analog design ow has been the same for the last three decades, Designers rely mainly
on intuition and experience along with an extensive use of simulators going back and
forth until a design point meets all the required speci cations. For long, a clear concise
path for systematically designing analog circuits was lost, leading to uninformed design
decisions and sup-optimal designs.
In this thesis, the Analog design of LDOs is automated with the aid of precomputed
look-up tables and an accurate symbolic solver. The gm/ID methodology is extended
to allow for capturing the layout-dependent eects in the Lookup tables. The used au-
tomation ow allows design space visualization and exploration in a systematic manner
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owing to the usage of the gm/ID methodology and takes PVT variations into consid-
eration. A design point ful lling the required speci cations can be chosen and veri ed
against the simulator. In addition, the automation ow is made more generic such that
the only required entry from the designer to automate an LDO topology is a netlist
with minimum restrictions.