الفهرس 
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Abstract
High-speed serial data links can be used in many wireline communication standards
as they solve synchronization problems resulting from using parallel data buses.
This thesis studies equalization techniques for 8 Gb/s at the receiver side. Two types
of equalizers are proposed, a linear equalizer mainly a continuous time linear equalizer
(CTLE) followed by a non-linear equalizer mainly decision feedback equalizer
(DFE). It describes the implementation issues in designing a 1-tap half rate currentintegrating
DFE. It presents the design both at the system and the circuit levels.
In addition, a new circuit technique for a CTLE called discrete-time linear equalizer
(DTLE) is introduced. The DTLE samples and amplifies the input data in a clock
phase then holds the output data in the other clock phase which is the integrating
phase of a current-integrating DFE. This amplify/hold technique eliminates 3.9dB
losses. The target application is low power SERDES working at a data rate of 8
Gb/s in 40nm CMOS technology and 1.1V supply with 4GHz half-rate clock. The
system doesn’t use any speculation techniques. Speculation techniques decrease the
requirements on the slicer delay which enables the system to work at higher speeds.
However, it increases area and power consumption of the system. It also increases
the load, and complicates the design of other receiver blocks like the clock and data
recovery (CDR) circuits. New circuit architecture is introduced to enable 8Gb/s
speed without speculation. This new architecture has higher speed and lower power
consumption. Combining these functionalities into one block decreases the overall
delay and improves the system performance. The decision feedback equalizer (DFE)
system consumes a power of 670uW and the discrete time linear equalizer (DTLE)
consumes 190uW at the half-rate. The equalization is shown to compensate for
channel losses up to 25dB from 25-inch FR4 channel with total power consumption
less than 1.1mW.
Key words: Equalization techniques, Decision feedback equalization, Continuous
time linear equalizer, High speed, DFE, CTLE, Sense amplifier flip-flop, Peaking
amplifier, lossy channel.
Publications:
Ismail, Ahmed; Ibrahim, Sameh; Dessouky, Mohamed,“A 8 Gbps 0.67mW 1 Tap
Current Integrating DFE in 40nm CMOS,” IEEE 57th International Midwest Symposium
on Circuits and Systems (MWSCAS), pp. 81-84, 3-6 Aug. 2014.
A.Ismail, S. Ibrahim and M. Dessouky, “An 8 Gbps Discrete Time Linear Equalizer,”
submitted to ISCAS 2015.
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